JD for FPGA/ ASIC Design lead Position

Note: We are looking for candidates who can join immediately or max 1 month.

POSITION: ASIC/FPGA RTL Design Lead:

LOCATION: Bangalore

QUALIFICATIONS: BE/B.Tech/ME/M.Tech

EXPERIENCE: 4-10 years

JOB DESCRIPTION:

Key Requirement:

1.      RTL designer (using Verilog or SystemVerilog) and good exposure to front-end design tools and flows.

2.      Good Knowledge in design of state machines, Datapath’s, arbitration and clock domain crossing logic.

3.      Good experience in ARM technologies and Integration of various subsystem blocks.

4.      Good experience in Low Power Design (UPF) design methodologies.

5.      Good experience in Synthesis, Constraint Development, Linting, CDC LEC and STA.

Optional:

6.      Experience in scripting like Shell, Perl, Python and PHP

7.      Knowledge of low-speed bus protocols (like SPI/QSPI, I2C, I2S & etc) and high-speed serial protocols (PCIe/USB/Ethernet) will be plus.